Fpga Turbo Series - Implementing A Uart

Develop a fully functional UART from start to finish and implement on your own FPGA development board
What you'll learn
Gain a solid understanding on how the UART protocol works.
Implement a fully functional UART on their FPGA development board.
Have a UART implementation in VHDL that they have created themselves.
Improve their skill sets in FPGA development platforms, specifically Vivado's Design Suite.
Able to interpret, design, and implement a complex state machine.
Requirements
Download and install Xilinx Vivado Design Suite.
Download and install TeraTerm or any other type of terminal emulator. There are instructions on how to install TeraTerm included in this course if you happen to get stuck.
Basic understanding or exposure to VHDL.
Basic understanding of digital circuits.
Familiar with what a Field Programmable Gate Array (FPGA) is.
Description
This course will explain how the Universal Asynchronous Receiver Transmitter (UART) protocol can be used to transmit and receive information. The UART protocol structure is explained in great detail with many visual representations to help the students understand how a UART works. Once the UART protocol has been sufficiently explained to the students, they will then be guided through the FPGA design and development process in order to implement a fully functional UART on their FPGA development boards. This fully functional UART will be able to accept commands received over the UART serial port and act upon these commands. These actions will include being able to individually select which LED's are on and which ones are off, as well as being able to set the number displayed on the 7 segment display.
Students will be provided with VHDL design files that can be used as starting points for their UART design. Working with the provided design files and using the lectures as references the students will implement a fully functional UART on their development boards. The students will get to use Xilinx's development tools for the design and debugging of their UART implementations.
This course is geared towards students who have been exposed to VHDL, FPGA's, as well as a basic understanding of digital circuits. This is a great supplement to any engineering student who wants to improve upon their hardware design skills before entering the workforce. This course is also great for anyone who is currently employed in the field engineering. Also any electronic hobbyist would benefit greatly from this course!
Upon completing this course students will have all the necessary design files to implement a UART on virtually any FPGA with minimal modifications. Beings that the students will be designing and debugging their own code they will have very detailed knowledge of how this design works and will easily be able to adapt it so that they can add support for many more commands!
Overview
Section 1: Introduction to the Course
Lecture 1 Introduction
Lecture 2 Board Compatibility
Section 2: Universal Asynchronous Receiver Transmitter (UART)
Lecture 3 Introduction to UART
Lecture 4 UART Protocol
Lecture 5 ASCII
Lecture 6 UART Transmission Example
Lecture 7 UART Verification
Section 3: UART Transmitter FPGA Design
Lecture 8 UART Transmitter Design
Lecture 9 UART Transmitter State Machine Design
Lecture 10 Creating UART Transmitter Vivado Project
Lecture 11 UART Transmitter Design Guide
Lecture 12 UART Transmitter Simulation and Verification
Section 4: UART Receiver FPGA Design
Lecture 13 UART Receiver State Machine Design
Lecture 14 Creating UART Receiver Vivado Project
Lecture 15 UART Receiver Simulation and Verification
Section 5: UART Controller FPGA Design
Lecture 16 UART Controller State Machine Design
Lecture 17 Creating UART Controller Vivado Project
Lecture 18 UART Controller Simulation and Verification
Section 6: UART Demonstration
Lecture 19 Programming the BASYS 3 Board
Lecture 20 UART Setup on the BASYS 3 Board
Lecture 21 UART Demonstration on the Basys 3
Section 7: Development Tools
Lecture 22 Download and install Xilinx Vivado Tool Suite
Section 8: Conclusion
Lecture 23 Conclusion
You should take this course if: You have completed my Learn VHDL and FPGA Development course,You should take this course if: You have prior experience working with VHDL and FPGA's ,You should take this course if: You have been exposed to VHDL and FPGA's,You should not take this course if: You have no prior VHDL, FPGA, or digital circuit knowledge
Screenshots


https://rapidgator.net/file/e7f83e6c78e0db717ad9edcb1d4af451/FPGA_Turbo_Series_Implementing_a_UART.part1.rar.html
https://rapidgator.net/file/eaa65de52a2633eaa69b034f467dd8eb/FPGA_Turbo_Series_Implementing_a_UART.part2.rar.html
https://rapidgator.net/file/2ae7b14fa4996400a7a5aa035e3f23f8/FPGA_Turbo_Series_Implementing_a_UART.part3.rar.html

https://uploadgig.com/file/download/d522013fedF9f635/FPGA_Turbo_Series_Implementing_a_UART.part1.rar
https://uploadgig.com/file/download/301c6f553fBac290/FPGA_Turbo_Series_Implementing_a_UART.part2.rar
https://uploadgig.com/file/download/236b764ddbe22355/FPGA_Turbo_Series_Implementing_a_UART.part3.rar