Cadence Sigrity and Systems Analysis 2022.1 HF002 (22.10.200)

Cadence Sigrity and Systems Analysis 2022.1 HF002 | 3.6 Gb
Product:Cadence Sigrity and Systems Analysis
Version:2022.1 HF002 (22.10.200) Hotfix Only
Supported Architectures:x64
Website Home Page :www.cadence.com
Languages Supported:english
System Requirements:Windows *
Software Prerequisites:Cadence Sigrity and Systems Analysis 2022.1 and above (link bellow)
Size:3.6 Gb
Cadence Design Systems, Inc., a leader in global electronic design innovation, is pleased to announce the availability of Sigrity and Systems Analysis 2022.1 HF002 (22.10.200) is a supplier of software for IC package physical design and for analyzing power integrity and signal integrity.

Sigrity and Systems Analysis 2022.1 HF002 (22.10.200) Release notes - Date: August 2022

Systems Analysis 2022.1 HF2
The following new features have been added in Celsius Thermal Solver in this release:
Celsius Thermal Solver Enhancements
-Post-Processing Enhancements
(New) For better and enhanced visualization of field Descriptions, a new GUI has been added in the Celsius Solid Objects Simulation for 3D Structures and Celsius Fluid Flow Simulation modules. The new GUI enables you to perform operations, such as Descriptionting on a slice, a line, and points on the 3D objects, viewing the warpage displacement, and Descriptionting results at different time step progressions. In addition, in the Celsius Fluid Flow Simulation module, you can view the velocity flow trajectory using the Streamline option.
-Material Manager Enhancements
(Enhanced) The following options have been added in the Material Manager window in the Celsius Solid Objects Simulation for Layered Structures module for better usability:
. Replace All from Library: Overwrites the materials in the design with matching materials in the material library.
. Filter by Name and Filter by Property: Filters the materials in the design/material library by their names or properties. When filtering by material property, you can also include or exclude certain materials from the search results.
. Clone: Creates a copy of an existing material.
-Support for Adaptive Time Stepping
(New) You can now use adaptive time stepping as the time step criteria in the Celsius Solid Objects Simulation for Layered Structures and the Celsius Solid Objects Simulation for 3D Structures modules. When using the adaptive time stepping criteria, the tool automatically introduces additional time steps (typically 10% of the existing time step size) whenever there is a change in the power gradient. This results in finer time steps that capture all power changes and lead to improved convergence and better accuracy.
-Non-uniform Time Stepping Criteria
(New) In the Celsius Solid Objects Simulation for Layered Structures and Celsius Solid Objects Simulation for 3D Structures modules, you can now specify non-uniform time steps as the time marching criteria. In non-uniform time stepping, you can divide the total simulation time into smaller chunks and specify variable time intervals for each chunk. You can set smaller intervals to capture rapid power changes and longer intervals when infrequent power changes are expected.
-Curve Descriptions Import from External Source
(New) You can now import curve Descriptions or simulation data from external sources into the curve view window in the Celsius Solid Objects Simulation for Layered Structures module. The imported curve Descriptions can be used to compare experimental data and draw inferences. The imported curve Description should be in .csv format and should have the same data type as the Celsius curve Description.
Sigrity 2022.1 HF2
Broadband SPICE
-Broadband SPICE Added to Layout Workbench
(New) In this release, Broadband SPICE has been added to Layout Workbench, and the appearance of the user interface has been enhanced. By default, Broadband SPICE now uses a dark application theme.
-Help Menu Update
(New) The Help menu for Broadband SPICE has been improved and is now consistent with other Layout Workbench tools.
PowerDC
-Specifying the Total Current in '%'
(Enhanced) While specifying an unequal current model in the Sink wizard, you can define the current in percentage (%). This will help you in distributing the current evenly to each node.
-Extracting PowerTree for Enabled Nets Exclusively
(Enhanced) Allows you to extract PowerTree from the opened design exclusively for the enabled power nets in the Net Manager.
-Exporting the Detailed Current Summary
(New) You can now export the detailed current summary for the BGA pad with each net in a separate sheet for the instances where the package and PCB are merged. This will help you in deciding whether the package and PCB design can be used.
-Search by Distance
(New) The Search Distance option allows you to group all ground net pins within this search distance (radius) into the negative terminal for each signal or power net in the circuit. You can use this option while defining a Sink or VRM.
-Reusing the SPD File Settings
(New) You can now reuse the PowerDC setup from one .spd file to another. This includes settings like VRMs/SINKs/Discretes/DC-DCs, and so on. This feature will let you copy the settings from the .spd file that you will load into the existing layout file
T2B
-T2B added to Layout Workbench
(New) In this release, T2B has been added to Layout Workbench, and the appearance of the user interface has been enhanced. By default, T2B now uses a dark application theme.
-Help Menu Update
(New) The Help menu for T2B has been improved and is now consistent with other Layout Workbench tools.
XtractIM
-Option for Setting the Return Path for Individual Nets
(Enhanced) In the Electrical Performance Assessment mode, you can select the return path for Power-Ground analysis for individual nets. All the enabled power and ground nets will be available in the Return Net drop-down menu of each net.
-PLOC Matching Support for Multiple Dies
(Enhanced) In the Pin-based Model Extraction, you can assign the Die Instance name for each component in a multi-die circuit. It helps you identify the components that belong to a chip. The Die Instance is set to the RefDes name by default. The output SPICE Model shows the node mapping between the .ckt node and the PLOC node of each RefDes component.
XcitePI
-Defining the MCP Connection Type
(New) You can define the MCP connection type for each layer as DIE or PKG. To define the MCP connection type, click on the MCP Connection Type column entry corresponding to a layer in the SPICE NETLIST form.
PowerSI and Clarity engines support automated extraction directly from Allegro Canvas
A new workflow will soon be integrated with Sigrity Aurora in the OrCAD and Allegro 17.4-2019 QIR4 release to enable greatly simplified and automated interconnect model extraction (IME). The PowerSI and Clarity engines have been enhanced in the Sigrity and Systems Analysis 2022.1 base release to facilitate this new workflow. Users that are licensed to run Sigrity Aurora II and Sigrity PowerSI II and/or Clarity 3D Solver will benefit from this integration when the following two releases are installed together:
- OrCAD and Allegro 17.4-2019 QIR4
- Sigrity and Systems Analysis 2022.1 base release
Cadence Sigrityprovides a rich set of gigabit signal and power network analysis technologies, including a unique power-aware signal integrity analysis capability for system, printed circuit board (PCB), and IC package designs. The combination of Sigrity analysis technologies with Cadence Allegro and OrCAD design tools will provide a comprehensive front-to-back integrated flow to enable system and semiconductor companies to deliver high-performance devices employing gigabit interface protocols such as DDR and PCI Express. The integrated solution will particularly benefit customers delivering electronic systems in high-growth markets such as mobile multimedia devices and cloud computing infrastructure.
Cadence Sigrity accurate signal integrity analysis for PCB
Here we see Cadence Sigrity in action. A thorough sign off tool dealing with signal integrity and power integrity at the PCB and IC Package level.
Cadence enables global electronic design innovation and plays an essentialrole in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers and research facilities around the world to serve the global electronics industry.