PathWave Advanced Design System (ADS) 2022 Update 1 (Win x64)

File and Workspace Management Tools
AEL Interfaces
- ADS platform's Message List docking window, used to display error or warning messages, is enhanced to accommodate arbitrary textual information. The text is presented with a leading "INFO:" tag. A new AEL API, info_message(), can be used to send the textual information to the Message List docking window.
- New AEL API, de_archive_workspace(), is added for archiving a workspace. For more information, see Workspace Management Functions.
Design Editing and Layout
General Enhancements
- Technology Scale Factor, an advanced feature used to scale instances in multi-technology workflows, can now be applied at the individual Smart Mount Pcell's cell level. For more information, see DXF Functions.
- Route spiral traces can easily be done with Trace > Avoid obstacles when routing (H)>Avoid same net (N) setting turned on.
- Enhanced Plane tool to support hierarchical global nets.
- Enhanced Design Differences tool to update parameters for all the components using a single command.
- Enhanced layout translators - ODB++, ABL, BRD and Gerber-to preserve arcs in paths and traces.
AEL Interfaces
- DXF translations can be fully automated via a new set of AEL APIs. For more information, see DXF Functions.
- A set of AEL APIs to enable options setting for GDSII translations launched from AEL APIs. For more information, see GDSII Functions.
- A set of AEL APIs to get and set attributes of OA vias, and to set the "Default" and "Stackable" parameters of an OA via definition. For more information, see Via Functions - OA.
- New AEL API, stack_trace(), is added for retrieving the AEL call stack information upon the invocation of this function call.
- New AEL API, getpid(), is added to retrieve the process ID for the ADS platform process.
- New or revised AEL APIs that enable Design Context to be specified:
. New AEL API, db_add_text_ex(), for creating text object in the specified designContext.
. New AEL API, db_convert_to_polygon_selected(), for polygon conversion operation to be performed on the selected objects in the specified designContext.
. New AEL API, db_flatten_selected(), for flattening operation to be performed on the selected objects in the specified designContext.
. New AEL APIs, db_mirror_x_selected(), db_mirror_y_selected(), and db_copy_and_paste_selected(), for editing operations to be performed on the selected objected in the specified designContext.
. de_boolean_logical_ex(), db_export_design(), de_crop() and de_union() enhanced to optionally take in designContext as a parameter.
Data Display
General Usability Enhancements
- A Message List docking window is newly introduced to Data Display window and can be optionally turned on or off. This window is where Data Display related error or warning messages are presented.
- The display properties of Legend data can now be configured by Legend's Options dialog box. The properties may be accessed by double clicking on the legend you want to change. For more information, see Changing Legend Properties.
- The display properties of the labels for swept values can now be configured in the Trace Options dialog box. The properties may be changed by selecting the "More..." button next to the "Display Label" checkbox on the Linear tab in the Trace Options dialog.
Data Viewing, Analysis and Manipulation
- Limit Lines now change color to indicate a pass or fail state. The Limit Line options dialog allows you to change the color, line type and thickness of the Limit Line pass or fail states. Limit Lines also support a pass/fail expression allowing you to create custom expressions that utilize the pass or fail state. For more information, see Limit Lines PASS or FAIL States section under Descriptions and Lists page.
- Limit Lines and Masks can be dragged from the Expression Manager, and dropped into existing rectangular Descriptions or for creating a new rectangular Description.
- Improved Expression Manager in organizing the objects in a Data Display, the data within a dataset, in presenting multiple datasets, in showing the detail information of a variable, and in its interaction with Variable Explorer.
- Improved Variable Explorer in presenting the contents of selected Variable(s).
- Fixed a Data Display crash when creating a quick Description window (AutoDescription).
Circuit Simulation
General
- Support of the Version 1.4 of BSIM BULK 106.2 (tmemod=1.4)
- HiSIM2 Version 3.11 is now supported.
- In Circuit Envelope, the fitting of S-Parameter data has been improved to be consistent over all S-Parameter formats description and grid (Citifiles, SIO, Touchstone,...).
- Two Josephson junction devices are now available in ADS 2022 Update 1.0
. One has two terminals, the other three. Though they behave identically, the third pin allows to observe or adjust the internal quantum phase of the device.
Obsolescence Announcement.
- The RF System Budget Analysis will be deprecated in ADS 2022 Update 2.0, and removed in ADS 2023.
ElectroThermal
- ETH_USER_DEF_TRSTEPS: Support of multiple test benches in same workspace. Each test bench may use a different arbitrary timestep file named___ETH_OUTER_STEP_TIMES.
- Smart mount is supported for Electrothermal (ETH) simulation (excluding the thermal Floor-planner).
HSD Design
SerDes
- Added TDR/TDT capability to S-Parameter Toolkit.
- New JMPOutput component that generates .csv file with input variables and simulation results used in JMP for Design of Experiments (DOE) analysis.
- Added the capability to load .setx configuration file for FlexDCA and Infiniium probes.
- Supports additional jitters in ReTimer_AMI components in Channel Simulation.
DDR/Memory
- New CA/Data Bus Designer beta product that helps designer engineers quickly build pre-layout designs for CA and Data bus.
- Added TDR/TDT capability to S-Parameter Toolkit. Improved the calculation speed for S-Parameter Causality check by multi-threading.
- Memory Designer now supports new DRAM type, NAND Flash.
- Added Single-Ended PAM4 eye height and eye width measurements to Design Exploration in Memory Probe.
- Supports memory interface simulation report generation in HTML format from "Design Exploration". The report will produce pass/fail data against user-entered limit values and Description any measurement specified in Memory Probe.
- New PCIe AMI Model Builder that generates Tx and Rx AMI models for PCIe applications.
- Improved smart component's wire connection with edge snapping.
- Added new VRM (Voltage Regulator Module) option to Memory Controllers and Memories.
- FIR taps entry method for equalization is added to the Tx model setup in Memory Designer.
- Improved DDR_Termination component warning when the associated PCB data is missing.
EM-SIPro/PIPro
SIPro
- Speed grades for GDDR6, GDDR6X and GDDR7 have been added to the DDR setup.
- Port editing is made easier. You can now drag and drop a pin onto an existing port pin to have it replaced. The polarity of the port pin will be preserved.
- Automated passivity check and passivity enforcement for SIPro S-parameter models, ensuring passive results in the calculated frequencies
- Improvements in coplanar ground detection in the RapidScan extraction
- Full support to incorporate surface roughness effects, including support for the Huray model.
PIPro
- New W3036E Conducted EMI (CEMI) for PIPro product is shipping with ADS2022 Update 1.0. PIPro CEMI Analysis includes dynamic switching models of the VRM that enable a full Conducted EMI test bench to be run from within PIPro or exported to ADS schematic. W3036E ships with Harmonic Balance to enable fast simulation of steady state time domain ripple and conducted EMI spectral content. The licensing element is e_pwd_pi_emi.
Obsolescence Announcement
- The Encrypted HSPICE is obsoleted.
EM Simulation
RFPro Platform Improvements
- HFSS Link
. Dot pins on an edge and edge pins (on an edge!) will be translated to an HFSS EdgeTerm. The HFSS Port Type will be set to 'Gap'. This is the equivalent of the FEM sheet port.
. The HFSS DeembedParasiticPortInductance flag will be enabled when the port's FeedType != DeltaGap.
- Port editing is made easier. You can now drag and drop a pin onto an existing port pin to have it replaced. The polarity of the port pin will be preserved.
- Design parameters from the top level OpenAccess or 3D EMPro component instances can be modified in RFPro what allows analyzing their impact.
RFPro EM Solver Improvements
- FEM Generation 2
. An issue has been fixed in RFPro-FEM Generation 2 to properly account for the conductivity (or resistivity) of sheet conductors.
. RFPro-FEM Generation 2 now supports surface roughness.
EM Simulation
Verification
- Design Rule Check
. ADS DRC supports over 40 new rules, including aspect ratio and center-point spacing.
. The rules syntax is simplified with single-word qualifiers.
. Polygon selection rules produce notes that show the actual value produced by the rule.
. DRC can be run on LVS Device Recognition rules. Device, pin and artwork layers appear as DRC errors and can be highlighted in the layout.
. Performance improvements.
- Layout Versus Schematic
. Improved highlighting of LVS errors such as unmatched nets.
. Component artwork can contain a pad stack with or without an additional area pin.
- PDK Validator
. PDK Validator can be configured to create test cells with more combinations of instance parameters.
. Progress dialog shows information on which tests are running.
. Cancel button is more responsive.
Design Kits
- The "iso" layer thickness was modified and set to 4nm. in the substrate file.
- Since the "iso" layer was already defined as a "sheet", this change in the thickness will not impact the EM results; the results will remain the same as before.
Power Electronics
PEPro
- New AC-DC test benches added for Voltage Spikes, Conducted EMI and Radiated EMI results.
- Speed up of 3D field data loading while visualizing Far Field results.
- Speed up of Circuit Simulation Dataset loading in the Near Field and Far Field results.
Netlist Translator
- Added support to expressions in SPICE compatible Inductor elements.
- Added support to an additional syntax when values are not enclosed in curly brackets, in SPICE compatible Capacitor elements specified in terms of their charge.
- Added support to node names with special characters in SPICE compatible Capacitor elements.
- Added a new translation rule to handle accuracy issues in ADS simulations when a SPICE compatible equation is in the form log(1+exp(x)).
- Added support to handle log functions with complex arguments during netlist import.
- Added support to an additional syntax where function name and its body are separated by an '=' in SPICE compatible .FUNC statements.
- Added support to translate SPICE compatible limit functions to ADS built-in limit_warn function, eliminating the need for including spice functions file during its simulation.
- Added support to node names with special characters in SPICE compatible Voltage Controlled Voltage Source and Voltage Controlled Current Source elements.
- Fixed warning message statement while importing a SPICE compatible MOSFET model card with its Length or Width specified.
- Fixed a bug where an additional comma was added to the end of the line while translating a SPICE compatible Options statement.
- Fixed a bug where unrecognized characters were sometimes printed in warning messages during netlist translation.
- Fixed a bug where an additional comma was added to the end of the line while translating a SPICE compatible Options statement.
Examples
- Added a new example to demonstrate the use of PEPro in simulating Single_Phase_Inverters i.e Half_Bridge and Full_Bridge inverters. Inverter is designed using PE library Components. For more information, refer Simulation of Single_phase_inverter Using PEPro.
- Added a new example to demonstrate the use of PEPro in simulating Three_Phase_Inverter. Inverter is designed using PE library Components. For more information, refer Simulation of Three_phase_inverter Using PEPro.
Power Electronics Library
- Added Voltage Tolerance and Time Tolerance parameters to Logic Gates. For more information, refer LTSpice Compatible Logic Gates.
Signal Processing
Obsolescence Announcement
- The DSPSource related features (e.g. DSP_To_ARF, 3GPPFDD_Dn/UpLink_src, TDSCDMA_Dn/UpLink_Src, WLAN_802_11a/b_Src) is deprecated and will be removed in ADS 2023 release.
Virtual Test Bench (VTB)
For general information about Virtual Test Bench (VTB), visit the VTB webpage athttp://www.keysight.com/find/virtual-test-bench.
From ADS 2022:
- Verification Test Bench (VTB) is now called Virtual Test Bench (VTB).
- To install files that are required for the VTB functionality along with the ADS installer, you need to download a separate VTB installer for both Windows and Linux and manually install the VTB.
- If you have already installed ADS and find VTB functionality is missing, then you need to download and manually install the VTB.
- If you want to uninstall, then you need to manually uninstall VTB separately for both Windows and Linux.


Keysight's PathWave, an open, scalable, and predictive software platform,offers fast and efficient data processing, sharing and analysis at every stage in the product development workflow. Combining design software, instrument control and application-specific test software, it enables engineers to address increasing design, test, and measurement complexity and develop optimal electronic products.
PathWave Advanced Design System (ADS)is the world's leading electronic design automation software for RF, microwave, and high-speed digital applications. ADS pioneers the most innovative and powerful integrated circuit-3DEM-thermal simulation technologies used by leading companies in the wireless, high-speed networking, defense-aerospace, automotive and alternative energy industries. For 5G, IoT, multi-gigabit data link, radar, satellite and high-speed switched mode power supply designs, ADS provides an integrated simulation and verification environment to design high-performance hardware compliant with the latest wireless, high speed digital and military standards.
PathWave Advanced Design System (ADS) 2022simulation software reduces design time and de-risks product development for DDR5, LPDDR5 and GDDR6 memory systems.
What's New in ADS 2022
This playlist provides a list of videos showing new or updated features/capabilities in PathWave Advanced Design System (ADS) 2022.
Keysight Technologies Inc.is the world's leading electronic measurement company, transforming today's measurement experience through innovations in wireless, modular, and software solutions. With its HP and Agilent legacy, Keysight delivers solutions in wireless communications, aerospace and defense and semiconductor markets with world-class platforms, software and consistent measurement science. The company's nearly 10,500 employees serve customers in more than 100 countries.