Synopsys SpyGlass vP-2019.06 SP1.1 with Documentation

Key Enhancements in SpyGlass P-2019.06-SP1-1
SpyGlass Core
The following enhancements have been made:
-Pragma Comments in .awl Files:Enhanced SpyGlass to support pragma comments in .awl files. Note that in .awl files, pragma comments can be specified with the # character only unlike in .swl files where pragma comments can be specified with both # and // characters. This support is available only for block waiver pragmas in .awl files. Inline waiver pragmas are not supported.
-moresimple report:Enhanced SpyGlass by adding two rules, named ReportObsoleteRules and ReportDeprecatedRules, to report obsolete and deprecated rules specified in a SpyGlass run in the moresimple.rptreport by default. Previously, SpyGlass generated a Warning message on the screen only if an obsolete or deprecated rule is included in a SpyGlass run.
SpyGlass CDC
The following enhancement has been made:
-Ac_coherency06a:Enhanced SpyGlass CDC by adding a rule, named Ac_coherency06a, to report signals that are synchronized multiple times in the same clock domain within same sequential depth. In addition, a parameter, named coherency_seq_depth, is introduced that controls the number of sequential elements beyond which the common source is detected by the Ac_coherency06a rule.

9001197100 How to disable rule checking in awl waiver files?
9001361147 Reporting use of deprecated rule
9001495175 Need coverage metrics for WAP model efficacy
9001495264 Enhancing Ac_coherency06 to find synchronizer beyond comb&seq cells
9001503467 W110 incorrectly reporting violation when parameterized port widths are matching
9001508871 SpyGlass power support enable_sdc_naming when using instance_trace
9001509261 ROADF wrongly reported as NA_CP0 even when CP is NOT 0
9001517518 Report an error message when wrong synthesis result on ICG path happen
9001519869 License queuing failure
9001523923 False SGDCWRN_127 getting flagged
9001525135 Reset_sync04 missing violation
9001525641 Eliminate Need To Set Variable SNPS_SWAVE_INTERNAL_CLKNAME
9001529762 NoGates rule reports unintended violations
9001535847 Ac_cdc01a missing in 2018.09-1(coming in 2018.09) around multi-FF lib sync_cell
9001536223 SpyGlass Crash while click on modular schematic
9001539522 Missing clock_info03a for scenario having cell primitives
9001540407 SYNTH_167 documentation needs beef-up
9001543951 Crash on SpyGlass PE
9001545328 CGE Regression: Enable Waveform signal missing.
9001545370 Unexpected negative switching power in IO PAD when run PEPWR01 rule
9001546723 sdcschema not working in RTLStim2Gate mapping
9001546863 SGPE annotation does not use provided mapping info
9001547223 CheckAlwaysCombSensList-ML doesn't report a violation
9001547313 Allow user to define fastest clock for Activity Analysis
9001547775 SpyGlass Lint is sticking because high register array
9001549196 Record name is not annotated in power_est flow
9001549198 PE run taking around 16hr to complete
9001551222 User defined clk i/p required for activity analysis in power_activity_check goal
9001551430 Inconsistency in number of messages with MultiMachine - Kernel
9001551631 Runtime/ Memory issue
9001552626 SpyGlass determines code is unreachable Synth5037
9001552737 False SYNTH_12608 violation
9001553801 SYNTH_5407 fail when designread
9001555718 SYNTH_5407 violation for unknown reason
9001556811 Turn ON syn_set_option merge_always_blocks 1 by default
9001558293 Abnormal termination
9001560896 When changing Fonts, the rule violation doesn't change its size in SpyGlass GUI
9001563467 W415_report is empty when overload the severity with error
9001564775 Casting leading to constant 0 evaluation of an assignment
9001566859 Eval shows SpyGlass failing where other tools do not
Synopsys' SpyGlass RTL signoff solutionis a design and coding guideline checker that delivers full chip mixed-language (Verilog, VHDL and SystemVerilog) and mixed representation (RTL & gate) capabilities to speed development of complex system-on-chip (SoC) designs. SpyGlass' GuideWare methodology, greatly enhances the designer's ability to check HDL code for synthesizability, simulatability, reusability, clock domain crossings, low power, timing constraints, testability and RTL/gate signoff. SpyGlass also integrates industry-standard best practices, as well as Synopsys' own extensive experience working with industry-leading customers.
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Synopsys, Inc. is the world leader in electronic design automation (EDA) softwarefor semiconductor design. The company delivers technology-leading semiconductor design and verification platforms and IC manufacturing software products to the global electronics market, enabling the development and production of complex systems-on-chips (SoCs). Synopsys also provides intellectual property and design services to simplify the design process and accelerate time-to-market for its customers. Synopsys is headquartered in Mountain View, California and has offices in more than 60 locations throughout North America, Europe, Japan and Asia.
Product:Synopsys SpyGlass
Version:vP-2019.06 SP1.1 with Documentation
Supported Architectures:x86_x64
Website Home Page :

www.synopsys.com

Languages Supported:english
System Requirements:Linux *
Size:8.2 Gb